The invention relates to electronic circuits, and, more particularly, to dynamic random access memories (DRAMs). In particular, the invention relates to the control of the read/rewrite accesses and the pre-charging of reference cells associated with memory cells of a DRAM.
The invention applies advantageously, but not limitingly, to so-called xe2x80x9cembeddedxe2x80x9d dynamic memories. That is, the invention relates to memories made jointly with other components by the same technological process and which are intended to be integrated together within an application specific integrated circuit (ASIC), for example.
In static random access memories (SRAMs), information stored therein remains stored indefinitely, i.e., at least as long as the memory remains energized. On the other hand, dynamic memories require a periodic refreshing of the information stored therein due, in particular, to the stray leakage currents which discharge the storage capacitance of each memory cell.
Among dynamic random access memory cells, particular mention is made here of those including one, two or three transistors. Conventionally, dynamic random access memories are arranged in rows and columns of memory cells. Each column includes a metallization commonly referred to as the xe2x80x9cbit linexe2x80x9d and an immediately adjacent bit line referred to as the reference bit line or xe2x80x9cbit line complement.xe2x80x9d Moreover, means for column-wise pre-charging provide pre-charging of the bit line and the reference bit line of the column before a read access of the memory. The bit line pre-charging and the pre-charging of the reference bit line are generally performed at a voltage equal to Vdd/2, where the supply voltage Vdd represents the storage voltage of a high state (typically a logic xe2x80x9c1xe2x80x9d) and 0 volts (ground) represents the storage voltage of a low state (typically a logic xe2x80x9c0xe2x80x9d).
Most DRAM memories use a row of so-called xe2x80x9creferencexe2x80x9d cells, also connected to the bit lines and the reference bit lines, to equalize the charges of the bit lines and the reference bit lines. The reference cells also maximize the average amplitude of the signal between 0 and 1. Other pre-charging means are also provided for pre-charging the row of reference cells. The pre-charging of the reference cells is also performed generally at Vdd/2.
During a read access of a memory cell connected to a bit line, this memory cell and the reference cell connected to the reference bit line are selected (i.e., activated). Then the sign of the voltage difference between the bit line and the reference bit line is detected to determine the logic content (0 or 1) of the memory cell. This detection is conventionally performed with the aid of a read/rewrite amplifier connected between the bit line and the reference bit line. This amplifier generally includes two looped-back inverters (forming a bistable flip-flop), each formed by two complementary transistors and controlled by two successive signals read and rewrite (commonly known as xe2x80x9csensexe2x80x9d and xe2x80x9crestore,xe2x80x9d respectively).
Upon activation of the restore signal, the datum read from the memory is rewritten, thereby refreshing the contents of this cell. A conventional memory structure of this kind has certain drawbacks. A first drawback lies in the value of the voltage for pre-charging the reference cells. Specifically, by reason of the stray leakage currents which discharge the storage capacitance of each cell storing a logic xe2x80x9c1xe2x80x9d (i.e., in N-channel metal-oxide semiconductor (NMOS) technology), the voltage of the bit line is less than Vdd when the memory cell is selected. Also, the voltage difference between the bit line and the reference bit line may be reduced thereby when reading the memory cell.
This is especially troublesome if this voltage difference becomes less than the offset voltage of the read/rewrite amplifier since this may lead to erroneous refreshing of the memory cell (i.e., a 1 is rewritten whereas a xe2x80x9c0xe2x80x9d is read and vice-versa). This problem may arise in a memory which remains inactive (i.e., without read access) for a relatively long time. It may also occur in an embedded DRAM memory for which the process used is geared more towards the speed of propagation of the signals, consequently leading to an increase in the leakage currents.
A second drawback of the structure of the above prior art device lies in the means used for providing the return to the pre-charge value of the reference cells. Specifically, this return is ensured by the use of a DC voltage generator which is common to all the reference cells. However, the design of such a generator is especially difficult due particularly to the considerable charging capacitance (typically 1024 reference cells each having a capacitance of 30 fF), of the large voltage excursion required, and of the high frequencies (e.g., 50-100 MHz for current generations of memory).
The design of such a generator is all the more difficult at low voltages, and the static consumption may be too high to attain the necessary performance. Furthermore, it is especially difficult to distribute the voltage generated across the entire memory by the stray capacitances and miscellaneous resistances. Additionally, the pre-charging operation is greatly dependent upon the data read or written. The invention addresses the above problems.
An object of the invention is to pre-charge the reference cells of a memory to a pre-charge value which makes reading of the data less sensitive to current leakage.
Another object of the invention is to avoid the use of a DC generator for establishing the pre-charge potential for the reference cells, i.e., for pre-charging these cells.
Yet another object of the invention is to provide a pre-charging mechanism which is effective at low voltages and relatively faster than prior art devices, thus providing an increase in the operating frequency of the memory.
According to the invention, a method is for controlling a read access of a memory cell of a memory plane of a dynamic random access memory. In such a memory, the memory cell is connected to a bit line of the memory plane and associated with a main reference cell connected to a reference bit line. This process includes a phase of reading and refreshing the contents of the memory cell and a phase of pre-charging the bit line, the reference bit line, and the main reference cell with a view to a subsequent read access.
In the course of the phase of reading and refreshing the memory cell, the main reference cell and a secondary reference cell connected to the bit line are activated. After having deactivated the two reference cells, the main reference cell and secondary reference cell are pre-charged to a final pre-charge voltage chosen to be less than or greater than (as a function of the NMOS or PMOS technology used, respectively) half the sum of the high-state storage voltage and the low-state storage voltage. This is done by linking the main reference cell and secondary reference cell to a capacitive line separate from the bit line and from the reference bit line and having a predetermined potential and a predetermined capacitive value.
The invention therefore uses a charge sharing mechanism for pre-charging the reference cells. This charge sharing mechanism is especially effective at low voltage. It is instigated locally, thus allowing an increase in performance (faster pre-charging). This gives rise to an increase in the operating frequency of the memory. It is therefore unnecessary to provide a DC generator to establish the pre-charge potential for the reference cells. As such, an economy of consumption as well as an area savings is achieved.
Moreover, charge sharing using a capacitive line having a predetermined potential and a predetermined capacitive value makes it possible to pre-charge the reference cells to a pre-charge voltage different from half the sum of the high-state storage voltage and the low-state storage voltage (typically different from Vdd/2). Thus, by way of example, the final pre-charge voltage of the reference cells may be equal to one third of the sum of the high-state storage voltage and of the low-state storage voltage (e.g., Vdd/3) for NMOS technology and to two thirds of this sum (i.e., 2Vdd/3) for P-channel MOS (PMOS) technology.
According to one embodiment, the two reference cells may be activated in the course of the reading and refreshing phase to pre-charge the two reference cells with two intermediate pre-charge potentials respectively equal to the high-state and low-state storage voltages. The refreshed memory cell and the two reference cells are then deactivated, before pre-charging the bit line and the reference bit line, and the two reference cells are linked to the capacitive metallization at the predetermined potential.
Stated alternatively, the refreshed memory cell and the reference cells are deselected (isolated from the bit lines). The main and secondary reference cells then remain charged to an opposite state, as are the bit lines. The bit line and the reference bit line are then pre-charged, e.g., to the voltage Vdd/2 by an equalization mechanism. The final pre-charge potential of the reference cells is then obtained by a mechanism for sharing charges between three elements, namely a reference cell in the high state, a reference cell in the low state, and the capacitive line pre-charged to the predetermined potential.
According to another embodiment, the two reference cells may be activated in the course of the reading and refreshing phase to pre-charge the two reference cells with two intermediate potentials respectively equal to the high-state and low-state storage voltages. Then the refreshed memory cell is deactivated while maintaining the two reference cells activated. The bit line and the reference bit line are pre-charged to a pre-charge voltage equal to half the sum of the high-state storage voltage and of the low-state storage voltage. The two reference cells are then deactivated and are linked to the capacitive metallization at the predetermined potential.
Stated otherwise, the refreshed memory cell is deselected but the reference cells remain connected to their respective bit line. The system including the bit lines and the reference cells is then pre-charged, e.g., by an equalization mechanism, to obtain a pre-charging of the bit line and of the reference bit line to the value Vdd/2. This equalization value is then independent of the datum read. The final pre-charge potential of the reference cells is then obtained by a sharing of charge between the reference cells previously pre-charged to Vdd/2, and the capacitive line is pre-charged to the predetermined potential.
Whichever embodiment is used, the main and secondary reference cells are activated in the course of the reading and refreshing phase in such a way to pre-charge them to two opposite states (intermediate potentials). They are then deactivated and linked to the pre-charged capacitive line of the predetermined potential. Moreover, whichever embodiment is used, the value of the final pre-charge potential of the reference cells is independent of the pre-charge voltage and of the capacitive value of the memory cells. It depends only on the high-state and low-state storage voltages.
The invention also relates to a dynamic random access memory (DRAM) device including a memory plane including columns (each of which is formed by a bit line) and a reference bit line. Rows of memory cells are connected to the bit lines and reference bit lines. The DRAM device may also include a controllable read/rewrite amplifier connected to each column of the memory plane, controllable means for column pre-charging connected to each column for pre-charging the bit line and the reference bit line of said column, and pairs of reference cells respectively connected to the bit lines and the reference bit lines of the columns. A main activation metallization of all the reference cells may be connected to the reference bit lines, and a secondary activation metallization of all the reference cells may be connected to the bit lines.
Furthermore, the DRAM device may include controllable means for pre-charging the reference cells. This controllable means may include pairs of linking transistors respectively connected between the pairs of reference cells, a control metallization for all the linking transistors, a capacitive metallization separate from the bit lines and from the reference bit lines and connected to all the respective common nodes of the pairs of linking transistors, and means for bringing the capacitive metallization to a predetermined potential. The means for pre-charging the reference cells may pre-charge (following a phase of reading and refreshing the contents of the memory cells of a row of the memory plane) the two reference cells of each pair to a final pre-charge voltage. The final pre-charge voltage may be chosen to be less than or greater than (as a function of the NMOS or PMOS technology used) half the sum of the high-state storage voltage and of the low-state storage voltage.
Moreover, the DRAM device may also include control means for controlling the read/rewrite amplifier, the means for pre-charging columns, and the means for pre-charging the reference cells. According to the invention, the control means are able to activate the main reference cell and the secondary reference cell of each pair during the phase of reading and refreshing the memory cells to pre-charge the reference cells respectively to two predetermined intermediate potentials. The control means are then able to deactivate the two reference cells and control the linking transistors to turn them on and to thus link the two reference cells of each pair to the capacitive metallization which has the predetermined potential. This is done to pre-charge the two reference cells to the final pre-charge voltage.
Additionally, the potential of the capacitive metallization may be zero. The means for pre-charging the reference cells may then include an auxiliary transistor controllable by the control means and able to link this capacitive metallization to ground. The capacitive metallization may include a metallization and a predetermined number of identical capacitors each having a capacitive value equal to that of the memory cell and all connected in parallel between the metallization and ground. When one wishes to obtain a pre-charge voltage for the reference cells equal to Vdd/3, for example, one may advantageously choose a number of identical capacitors equal to the number of columns.